1. Field of the Invention
The present invention relates to a zero-buffer circuit for a spread spectrum clock (SSC) system and a method therefor and more specifically, to a zero-delay buffer circuit having a delay-locked loop (DLL) based zero-delay buffer.
2. Background of the Related Art
In a related art of improving computer system efficiency, it is desirable to increase a processing speed by operating a central processing unit (CPU) at a higher frequency by increasing a clock frequency. An increase in clock frequency increases a frequency of the computer system, as peripherals (e.g., memory, graphic card) can also operate at a higher frequency. However, as the clock frequency increases, electromagnetic emission (EMI) increases due to an increased peak amplitude. As a result, EMI limits clock frequency improvements in the related art.
A related art technique known as spread spectrum clocking (SSC) reduces EMI and allows for an increased clock frequency by modulating the clock frequency along a modulation profile having a predetermined frequency. Because amplitude is reduced by the frequency modulation, EMI can be reduced while allowing an increase in the clock frequency. FIG. 1 illustrates a non-modulated spectral energy distribution 3 compared to the related art SSC frequency-modulated spectral energy distribution 1. A magnitude Δ of EMI reduction is determined by a modulation amount δ and a shape of the SSC spectral energy distribution 1.
FIG. 2 illustrates a related art modulation profile 9 used with the SSC technique. An SSC clock is modulated between a nominal frequency 5 of the constant-frequency clock fnom, and a down-spreading frequency (1−δ) fnom 7, where δ represents a spreading magnitude as a percentage of the nominal frequency fnom 5. The modulation profile 9 determines the shape of the SSC spectral energy distribution 1.
FIG. 3 illustrates a related art computer system that applies the related art SSC technique. In a motherboard 15, an SSC generator 11 receives an unmodulated clock input signal and generates a frequency-modulated clock signal in a first phase-locked loop (PLL) 13. The frequency-modulated clock signal is transmitted to a central processing unit (CPU) 17 and a peripheral board 19.
FIG. 4 illustrates a block diagram of the SSC generator 11. A first divider 49 receives the unmodulated clock input signal and generates an output received by the first PLL 13. In the first PLL 13, a first phase detector 35 receives an output signal of the first divider 49 and an input signal from a feedback divider 43 to generate an output signal that provides a measurement of a phase difference between the unmodulated clock input signal and the frequency-modulated signal. A first charge pump 37 receives the output signal of the first phase detector 35. The first charge pump 37 then generates charges in response to the output signal of the first phase detector 35. When a first loop filter 39 receives the charges from the first charge pump 37, the first loop filter 39 produces a DC voltage output. The DC voltage output of the first loop filter 39 is received by a first voltage controlled oscillator (VCO) 41. The first VCO 41 generates an output signal to a post divider 45 and the feedback divider 43. The post divider 45 then generates the frequency-modulated clock signal that is transmitted to the CPU 17 and the peripheral board 19, and the feedback divider 43 generates a reference signal for the first phase detector 35.
As shown in FIG. 3, the peripheral board 19 further processes the frequency-modulated clock signal in a zero-delay clock buffer 21 to generate an output clock signal for a peripheral device 23 (e.g., SDRAM, accelerated graphics port, etc.). The zero-delay clock buffer 21 includes a second PLL 25 having a second phase detector and a frequency detector 27, a second charge pump 29, a second loop filter 31, and a second voltage-controlled oscillator (VCO) 33.
However, the related art SSC technique has various disadvantages. For example, a jitter problem occurs due to a difference in period between a maximum frequency and a minimum frequency. As the input clock signal migrates from the non-modulated frequency over the modulation period, a change in period size occurs over clock cycles during a modulation event.
A skew problem also exists in the related art SSC technique due to a period difference between the frequency-modulated clock signal and the output clock signal. Because the output clock cannot be updated instantaneously, a period difference between the frequency-modulated clock signal from the motherboard 15 and the output clock signal to the peripheral device 23 develops. The cumulative effect of the period difference results in a significant phase error known as skew.
The skew and jitter of the related art SSC technique can be reduced by maximizing a bandwidth of the feedback loop in the second PLL 25 and minimizing a phase angle of an input-to-output transfer function of the modulation frequency. FIGS. 5 and 6 illustrate a relationship between increased feedback loop bandwidth, decreased phase angle, and decreased skew. However, even the related art SSC technique having optimized feedback loop bandwidth and phase angle still has the jitter and skew errors as discussed in Zhang, Michael T., Notes on SSC and Its Timing Impacts, Rev. 1.0, February 1998, pp. 1–8, which is incorporated by reference. Thus, the jitter and skew problems limit the clock frequency improvements that can be achieved by the related art SSC technique.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.